The present invention relates to methods of forming a semiconductor DRAM device with a buried capacitor. More specifically, the invention is directed to processes for fabricating a capacitor and a bit line conductor on opposite sides of a silicon-on-insulator substrate containing access transistors in which a self-aligned contact is preserved throughout the entire fabrication process. The invention also relates to the structures formed according to the processes hereinafter set forth.
In today""s semiconductor industry, the trend is increasingly towards denser arrays of components in a more compact area. However, as shown in FIGS. 1A and 1B, as capacitors 1 are brought closer together, the decrease in space between them necessitates that they be taller in order to provide the same capacitance value. Unfortunately, this means that a much deeper and narrower contact, e.g., a higher aspect ratio opening must in turn be provided for the digit or bit line plug 2 which must reach the transistor drain or source region in the substrate. The taller and more narrow the contact opening the harder it becomes to adequately xe2x80x9cmetallizexe2x80x9d the contact with the plug and other conductive material.
A few attempts to solve this problem have involved the formation of capacitors and bit lines on opposite sides of a supporting substrate. For example, S. Nakamura et al. in their article xe2x80x9cGiga-bit DRAM cells with low capacitance and low resistance bit-lines on buried MOSFET""s and capacitors by using bonded SOI technology-Reversed-Stacked-Capacitor (RSTC) Cellxe2x80x9d, IEDM 95-889, pp.35.4.1-35.4.4 (1995) describe a process of fabrication in which the capacitor is first formed on a substrate and then buried in insulative material. Thereafter, a supporting substrate is bonded to the insulative material, and the entire wafer is then xe2x80x9cflippedxe2x80x9d or turned over. SOI (silicon-on-insulator) formation followed by bit line formation completes the wafer fabrication process.
Other attempts at capacitor structure have been proposed by Nishihara et al. in xe2x80x9cA Buried Capacitor DRAM Cell with Bonded SOI for 256 M and 1 Gbit DRAMsxe2x80x9d, IEDM 92-803, pp. 32.3.1-32.2.4 (1992); B. H. Lee et al. xe2x80x9cA Novel Pattern Transfer Process for Bonded SOI Giga-bit DRAMsxe2x80x9d, Proceedings 1996 IEEE International SOI Conference, 96 CH 35937, October 1996; and Kim et al. xe2x80x9cAdvanced Integration Technology for a Highly Scalable SOI DRAM with SOC (Silicon-On-Capacitors)xe2x80x9d IEDM 96-605, pp. 22.5.1-22.5.4 (1996). In the latter Kim et al. article, fabrication proceeds by capacitor formation, wafer bonding, SOI formation, and then transistor and bit line formation.
All the foregoing methods, however, in addition to other problems also suffer from the fact that the digit or bit line contact formed after the wafer is xe2x80x9cflippedxe2x80x9d and then planarized is no longer self-aligned to the word line. This results in a significantly larger cell size for a given photolith capability. In other words, in the methods currently known in the art where the storage capacitor is formed on one side of the device, and then the device is xe2x80x9cflippedxe2x80x9d over and the digit contact is formed on the other side (or where the digit contact is formed first, and then the storage contact), only one of these contacts can be formed with a self-aligned contact (SAC) etch such that it is spaced away from the word line or gate electrode by the width of the spacer material. The other contact (on the opposite side to the word line or gate electrode) is thus not defined by the width between spacers, nor set exactly a spacer width away from the word line.
What is therefore needed in the art are more suitable methods of semiconductor wafer fabrication to provide more compact arrays of memory cells. More specifically, what is needed is a process of forming capacitors in which the starting substrate is first SOI processed and the self-aligned contact is preserved relative to the digit or bit line on both sides of the wafer throughout the entire fabrication process. Also needed are new structures afforded by these processes.
The method provides a method of fabricating a memory cell in which an access transistor is first formed on an SOI substrate. The access transistor is formed with source and drain regions in a semiconductor material layer of the substrate and has at least one gate stack which includes a gate region electrically connected with a word line. Also formed on a first side of the substrate is at least one capacitor which is electrically connected to one of the source and drain regions. At least one bit line conductor is formed on a second side of the substrate, which is opposite the first side. The bit line conductor is electrically connected to the other of the source and drain regions. At least one self-aligned contact plug connects at least one of the capacitor or the bit line conductor to the respective source or drain region.
Further provided as part of the invention is a method of fabricating a memory cell which comprises forming at least one transistor on a semiconductor substrate, such that the transistor has a source and drain region and at least one gate stack. Also formed is at least one capacitor connection plug which extends into the substrate and which is electrically coupled to one of the source and drain regions.
Further formed on the substrate is at least one bit line contact plug which is electrically connected to the other of the source and drain regions. In addition, a wiring connect is formed in contact with the bit line contact plug. A capacitor is then formed on an opposite side of the substrate to the side on which the bit line contact plug and wiring connect has been formed, such that the capacitor is electrically connected to the capacitor connection plug. At least one of the capacitor connection plug and the bit line contact plug is a self-aligned contact plug.
In a further embodiment there is provided a method of fabricating a memory cell, in which at least one transistor is first formed on a semiconductor substrate to have source and drain regions and at least one gate stack. At least one bit line contact plug is then formed into the substrate and is electrically connected to one of the source and drain regions. Also formed on the substrate is at least one capacitor connection plug which is electrically connected to the other of the source and drain regions. A capacitor is then formed over the capacitor connection plug and is electrically connected thereto. A wiring connect is then formed to the bit line contact plug on an opposite side of the substrate to the side on which the capacitor is formed. At least one of the capacitor connection plug and the bit line contact plug is a self-aligned contact plug.
The methods of the invention hereinafter described contemplate self-aligned contact etching of at least one, and preferably both of the bit line and capacitor connection contacts or plugs. In a preferred embodiment of the invention, these contacts are preserved throughout the entire fabrication process and even more preferably, are separated from their respective gate stacks by only the width of a spacer film which overlays the sides of the gate stacks.
The invention also provides a semiconductor device which is suitable for use as a memory cell. The device comprises a substrate, and an access transistor which has been formed on the substrate. The access transistor contains source and drain regions in a semiconductor material layer of the substrate. The access transistor also includes at least one gate stack with a gate region electrically connected with a word line. In addition, there is at least one capacitor formed on a first side of the substrate which is electrically connected to one of the source and drain regions. The device also contains at least one bit line conductor which has been formed on a second side of the substrate, which is opposite said first side. The bit line conductor is electrically connected to the other of the source and drain regions via a bit line contact plug. A capacitor connection contact or plug connects the capacitor to one of the source and drain regions. The capacitor connection plug and/or the bit line contact plug are preferably self-aligned contacts which are contained in self-aligned contact openings between gate stacks on the substrate, and even more desirably are separated from their respective gate stacks by the width of a spacer film which covers at least part of the sides of the gate stacks.
Additional advantages and features of the present invention will become more readily apparent from the following detailed description and drawings which illustrate various embodiments of the invention.